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| CXD1261AR Sync Signal, Timing Signal Generator for CCD Cameras Description The CXD1261AR is an IC which generates the sync signals and timing signals required for a camera system that uses the monochrome CCD image sensor (760H) such as the ICX038/039 and ICX058/059. Features * Compatible with monochrome (EIA/CCIR) systems * Built-in electronic shutter function * Built-in driver for the horizontal (H) clock * Built-in SG and TG functions Applications CCD camera systems Structure Silicon gate CMOS Absolute Maximum Ratings (Ta = 25C, Vss = 0V) * Supply voltage VDD VSS - 0.5 to +7.0 * Input voltage VI Vss - 0.5 to VDD + 0.5 * Output voltage VO Vss - 0.5 to VDD + 0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 5.0 0.25 * Operating temperature Topr -20 to +75 64 pin LQFP (PIastic) V V V C C V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95735B7Y-PS CXD1261AR Pin Configuration PBLK CLP4 CLP3 CLP1 CLP2 TST8 TST7 TST9 TST6 TST5 TST4 SHD SHP 32 VSS 31 XV4 30 XSG2 29 XV3 28 XSG1 27 XV1 26 XV2 25 XSUB 24 VDD 23 RG 22 VSS 21 TST3 20 H2 19 TST2 18 H1 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VR/FLD 49 HTSG 50 VDD 51 EXT 52 VSS TST10 53 54 TST11 55 VDD 56 TST12 57 TST13 58 VSS 59 TST14 60 TST15 61 TST16 62 CBLK 63 SYNC 64 HR VSS TST1 OSCI TRIG OSCO CKIN D1 HD D2 VSS ED0 ED1 ED2 VD ENB Mode name D1 D2 ENB ED0 ED1 ED2 PS EXT TST1 TST13 Pin No. 4 5 12 13 14 15 16 52 6 58 PRESET L L H H H H H L -- -- L EIA Field readout Normal H CCIR Frame readout Shutter Shutter speed Serial input Internal Parallel input External Normally High Normally Low Note) Normally open for TST except as shown in the above table. During frame accumulation (readout), low-speed shutter does not operate normally. -2- PS CL CXD1261AR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol HD VD CL D1 D2 TST1 TRIG VSS OSCI OSCO CKIN ENB ED0 ED1 ED2 PS VDD H1 TST2 H2 TST3 VSS RG VDD XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 VSS I/O O O O I I I I -- I O I I I I I I -- O I O I -- O -- O O O O O O O -- Horizontal drive pulse Vertical drive pulse CKIN 2 frequency divided output (EIA: 14.318MHz, CCIR: 14.1875MHz) Mode switching; low: EIA; high: CCIR (with pull-down resistor) Mode switching; low: field readout; high: frame readout (with pull-down resistor) Test input, fixed to high Shutter speed setting pulse (with pull-up resistor) GND Oscillating cell input Oscillating cell output Clock input (EIA: 28.636MHz, CCIR: 28.375MHz) Shutter switching; low: normal; high: shutter (with pull-up resistor) Shutter speed control (with pull-up resistor) Shutter speed control (with pull-up resistor) Shutter speed control (with pull-up resistor) Shutter speed setting method switching; low: serial; high: parallel (with pull-up resistor) Power supply Horizontal register drive clock Test input, normally open (with pull-down resistor) Horizontal register drive clock Test input, normally open (with pull-down resistor) GND Reset gate pulse Power supply Discharge pulse Vertical register drive clock Vertical register drive clock Sensor charge readout pulse Vertical register drive clock Sensor charge readout pulse Vertical register drive clock GND Description The CCD image sensor characteristics are guaranteed for field accumulation operation. -3- CXD1261AR Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol SHP SHD TST4 TST5 TST6 TST7 TST8 VSS CLP1 CLP2 CLP3 CLP4 PBLK TST9 VDD HR VR/FLD HTSG VDD EXT VSS TST10 TST11 VDD TST12 TST13 VSS TST14 TST15 TST16 CBLK SYNC I/O O O O O O O O -- O O O O O O -- I I I -- I -- I O -- O I -- O O O O O Description Precharge level sample-and-hold pulse Data sample-and-hold pulse Test output, normally open Test output, normally open Test output, normally open Test output, normally open Test output, normally open GND Clamp pulse Clamp pulse Clamp pulse Clamp pulse Blanking cleaning pulse Test output, normally open Power supply H reset pulse V reset pulse (FLD output when EXT = low) HTSG input; low: XSG1, 2 on; high: off (valid only when EXT = low) Fixed to low when EXT = high Power supply Sync mode switching; low: internal; high: external sync (with pull-down resistor) GND Test input, normally open (with pull-down resistor) Test output, normally open Power supply Test output, normally open Test input, fixed to low GND Test output, normally open Test output, normally open Test output, normally open Composite blanking pulse Composite sync pulse -4- CXD1261AR Block Diagram CL 63 64 H Counter 1/910 or 1/908 Decoder 1 2 Pulse Generator V Counter 1/525 or 1/625 45 CBLK SYNC HD VD Decoder PBLK 41 EXT HR VR/FLD HTSG 52 48 49 50 HTSG FLD 27 26 ENB PS ED0 ED1 ED2 TRIG 12 16 13 14 15 7 Shutter Control XSUB 29 31 28 30 25 Reset Generator 42 43 CLP1 CLP2 CLP3 XV1 XV2 XV3 XV4 XSG1 XSG2 XSUB OSCI 9 23 18 RG H1 H2 SHP SHD OSCO 10 11 CKIN 20 33 CL 1/2 High-speed Pulse Generator 34 CL 3 D1 D2 4 5 Mode Setting -5- CXD1261AR Electrical Characteristics 1) DC characteristics Item Supply voltage Input voltage Output voltage 1 1 Output voltage 2 2 Output voltage 3 3 Output voltage 4 4 Feedback resistor Pull-up resistor Pull-down resistor Symbol VDD VIH1 VIL1 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RFB RPU RPD IOH = -2mA IOL = 4mA IOH = -4mA IOL = 8mA IOH = -8mA IOL = 8mA IOH = -2mA IOL = 2mA VIN = VSS or VDD VIL = 0V VIH = VDD 500K 40K 40K 2M 100K 100K VDD/2 VDD/2 5M 250K 250K VDD - 0.5 0.4 VDD - 0.5 0.4 VDD - 0.5 0.4 (VDD = 5V 0.25V, Topr = -20 to +75C) Conditions Min. 4.75 0.7VDD 0.3VDD Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V 2) I/O pin capacitance Item Input pin capacitance Output pin capacitance Input/output pin capacitance Symbol CIN COUT CI/O (VDD = V1 = 0V, fM = 1MHz) Min. Typ. Max. 9 11 11 Unit pF pF pF Note) 1 CLP1, CLP2, CLP3, CLP4, PBLK, CBLK, SYNC, VR, HD, VD, XSUB, XSG1, XSG2, XV1, XV2, XV3, XV4 2 CL, RG, SHP, SHD 3 H1, H2 4 OSCO -6- CXD1261AR External Reset Description H Reset (HR) The reset is performed at the first falling edge of the reset pulse that was input; resets are not performed at subsequent edges as long as they do not deviate by two clock pulses (0.14s) or more. The minimum reset pulse width is 0.35s. In addition, HD immediately after a reset can not be guaranteed. The position at which the reset is performed is 2.31s advanced after the H reset input. H reset input 0.35s or more HD output 2.31s V Reset (VR) The falling edge of V reset pulse that was input is field identified by the phase difference with the internal signal (field judge pulse) defined by the falling edge of HD. And VD is reset in phase with V reset pulse. When field judge pulse is low and V reset pulse falls, EIA: VD falling edge after 262.5H is the relation between HD and VD of EVEN field. CCIR: VD falling edge after 313.5H is the relation between HD and VD of ODD field. Also, when field judge pulse is high and V reset pulse falls, EIA: VD falling edge after 262.5H is the relation between HD and VD of ODD field. CCIR: VD falling edge after 313.5H is the relation between HD and VD of EVEN field. The minimum reset pulse width is 64s. 262 (312) 263 (313) 264 (314) The value without ( ) is for EIA The value in ( ) is for CCIR 1 HD output Field judge pulse 2 3 VR input 64s or more VD timing is genarated after 262.5H with this VR timing VD output (EIA) VD timing is genarated after 313.5H with this VR timing 1HD VD output (CCIR) 1HD Note: For CCIR, VD output is delayed 1HD in relation to VR input. -7- CXD1261AR Electronic Shutter Description (During frame accumulation, low-speed shutter does not operate normally.) The XSUB pulse timing changes according to the electronic shutter control described below. In addition, the ENB pin controls whether the XSUB pulse is output or not; this control has priority. 1. Continuously variable shutter (trigger mode) * When using the normal shutter, either leave the TRIG pin open or connect it to the power supply. * When using the continuous variable shutter, input the clock pulse to the TRIG pin. VD HD XSG1 TRIG XSUB Shutter speed The shutter speed is determined by sampling the XSUB pulse during the interval between the falling edge of XSG1 and the falling edge of TRIG, and then stopping the XSUB pulse during the interval between the falling edge of TRIG and the next falling edge of XSG1. When using the TRIG pin to control the shutter speed, in order to broaden the control range it is necessary to use the ED0, 1, and 2 pins (described later) to set the shutter speed to 1/10000. 2. Normal shutter 2-1. Switching between parallel input and serial input Parallel input or serial input can be selected as the method for inputting the data used to determine the shutter speed. * Parallel input (PS = High): Permits selection of eight shutter speeds by using three bits ED0, ED1, and ED2. * Serial input (PS = Low): Shutter speed is determined by inputting the strobe to ED0, CLK to ED1, and the data to ED2. -8- CXD1261AR 2-2. When using parallel input (PS = High) Shutter speed table Only the high-speed shutter is used when using parallel input (During frame accumulation, low-speed shutter does not operate normally.) D1 X L H L H X X X X X X ENB L H H H H H H H H H H ED0 X H H L L H L H L H L ED1 X H H H H L L H H L L ED2 X H H H H H H L L L L Shutter speed Shutter off 1 1/60 (s) 1/50 (s) 1/100 (s) 1/120 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2 2 1 XSUB (shutter pulse) is not generated. 2 Accumulation time is as follows regardless of field accumulation/frame accumulation. D1 = Low (EIA), 1/60 (s) D2 = High (CCIR), 1/50 (s) (Pseudo field readout during frame accumulation.) 2-3. When using serial input (PS = Low) The following four modes can be selected according to the combination of serial data SMD1 and SMD2. (During frame accumulation, low-speed shutter does not operate normally.) Shutter mode Mode SMD1 SMD2 Flickerless L L High-speed shutter L H Low-speed shutter H L No shutter H H * Flickerless: Eliminates flicker resulting from the frequency of fluorescent light * High-speed shutter: Higher speed shutter than 1/60 (EIA), 1/50 (CCIR) * Low-speed shutter: Lower speed shutter than 1/60 (EIA), 1/50 (CCIR) (Does not operate normally during frame accumulation.) * No shutter: No shutter operation ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) The data on ED2 is latched in the register at the rising edge of ED1 and is then taken in internally while ED0 is low. -9- CXD1261AR ED2 tS2 th2 ED1 tS1 tS0 ED0 tW0 Symbol tS2 th2 tS1 tWO tSO ED2 setup time against the rising edge of ED1 ED2 hold time against the rising edge of ED1 ED1 rising setup time against the rising edge of ED0 ED0 pulse width ED0 rising setup time against the rising edge of ED1 Min. 20ns 20ns 20ns 20ns 20ns Max. -- -- -- 50s -- Low-speed shutter (Does not operate normally during frame accumulation.) FLD N = 2 x (1FF16 - L16) However, 1FF cannot be used as the load value. Load value 1FE16 1FD16 : 10116 10016 Shutter speed (FLD) 2 4 : 508 510 - 10 - Timing Chart (EIA) ODD FIELD EVEN FIELD HD VD SYNC CBLK FLD - 11 - EVEN FIELD ODD FIELD HD VD SYNC CBLK FLD CXD1261AR Timing Chart (CCIR) ODD FIELD EVEN FIELD HD VD SYNC CBLK FLD - 12 - EVEN FIELD ODD FIELD HD VD SYNC CBLK FLD CXD1261AR CXD1261AR Timing Chart (EIA) 1/2H 0 HD 21 HSYNC S Y N C 56 EQ 406 VSYNC 154 CBLK 861 476 511 91 1H 910 VD FLD Unit: clock pulses Timing Chart (CCIR) 1/2H 0 HD 21 HSYNC S Y N C 56 EQ 405 VSYNC 167 CBLK 859 475 510 91 1H 908 VD FLD Unit: clock pulses - 13 - Timing Chart (EIA vertical direction) ODD Field FLD CBLK/VD HD XSG1 XSG2 XV1 XV2 FIELD XV3 - 14 - XV4 XV1 XV2 FRAME XV3 XV4 PBLK CLP1 CLP2 CLP3 CLP4 CXD1261AR Timing Chart (EIA vertical direction) EVEN Field FLD CBLK/VD HD XSG1 XSG2 XV1 XV2 FIELD XV3 - 15 - XV4 XV1 XV2 FRAME XV3 XV4 PBLK CLP1 CLP2 CLP3 CLP4 CXD1261AR Timing Chart (CCIR vertical direction) ODD Field FLD CBLK/VD HD XSG1 XSG2 XV1 XV2 FIELD XV3 - 16 - XV4 XV1 XV2 FRAME XV3 XV4 PBLK CLP1 CLP2 CLP3 CLP4 CXD1261AR Timing Chart (CCIR vertical direction) EVEN Field FLD CBLK/VD HD XSG1 XSG2 XV1 XV2 FIELD XV3 - 17 - XV4 XV1 XV2 FRAME XV3 XV4 PBLK CLP1 CLP2 CLP3 CLP4 CXD1261AR Timing Chart (EIA horizontal direction) HD CK CL H1 H2 RG SHP SHD - 18 - XV1 XV2 XV3 XV4 XSUB CLP1 CLP2 CLP3 CLP4 PBLK The black-pointed sections of the H1 clock indicate the optical black. CXD1261AR Timing Chart (CCIR horizontal direction) HD CK CL H1 H2 RG SHP SHD XV1 - 19 - XV2 XV3 XV4 XSUB CLP1 CLP2 CLP3 CLP4 PBLK The black-pointed sections of the H1 clock indicate the optical black. CXD1261AR Readout Timing Chart (EIA) HD ODD XV1 XV2 XV3 578 36 36 36 3 XV4 FIELD READOUT EVEN XV1 XV2 XV3 XV4 XSG1 - 20 - 22 36 36 3 33 36 3 XSG2 ODD XV1 XV2 XV3 XV4 FRAME READOUT EVEN XV1 XV2 XV3 XV4 Unit: clock pulses (1ck = 69.84ns) CXD1261AR Readout Timing Chart (CCIR) HD ODD XV1 XV2 XV3 589 36 36 36 3 XV4 FIELD READOUT EVEN XV1 XV2 XV3 XV4 XSG1 XSG2 22 36 - 21 - 36 3 33 36 3 ODD XV1 XV2 XV3 XV4 FRAME READOUT EVEN XV1 XV2 XV3 XV4 Unit: clock pulses (1ck = 70.48ns) CXD1261AR CXD1261AR Timing Chart (High-speed phase) CKIN CL H1 H2 RG SHP SHD Application Circuit Signal processing 48 49 33 32 CCD image sensor CXD1261AR 64 1 17 16 Shutter control OSC EIA : 28.6363MHz CCIR : 28.375MHz Use a crystal that operates with a fundamental wave. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 22 - V Driver CXD1261AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 0.2 48 49 10.0 0.1 33 32 A 64 1 0.5 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03 + 0.05 0.127 - 0.02 0.1 0.1 0.1 0 to 10 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g - 23 - 0.5 0.2 (11.0) |
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